The invention relates to measuring signals in a tester system.
Tester systems for testing high speed devices, such as microprocessors and microcontrollers, have increasingly become more sophisticated due to high speed requirements. Referring to FIG. 1, a prior art timing measurement unit (TMU) 20 is used in a tester system 8, such as the ITS 90000GX system made by Schlumberger Technologies, Inc. A device under test (DUT) 10 is connected to a pin electronics (PE) card 12 in the tester system 8. The PE card translates signals received in the tester system 8 into DUT logic levels and converts signals received from the DUT 10 to test system signals, such as formatted ECL wave forms. Signals from the PE card 12 are passed to pin slice electronics cards 14, which in turn drive signals that are transmitted to corresponding high speed interface cards 16. Each high speed interface card 16 outputs a pair of signals HSPATHA and HSPATHB to a multiplexer 18, which selects the outputs from one of the high speed interface cards for output as signals MA and MB.
The selected pair of signals MA and MB are routed to TMU 20, which measures the time difference between signals MA and MB, or between corresponding pairs of signals from other sources 21 (such as signals used during calibration of the tester system 8).
Referring to FIGS. 2 and 3, the coarse difference between selected inputs TRIGA and TRIGB (which correspond to events to be measured, e.g., MA and MB) is measured by a coarse counter 110. The coarse counter 110 is clocked by a divide-by-four clock CCCLK having a frequency of about 62.5 megahertz (MHz), which is buffered from a divide-by-four clock CCLK from a programmable frequency divider 116. The coarse counter 110 starts counting on the first leading edge of CCCLK after activation of TRIGA and stops counting on the first leading edge of CCCLK after activation of TRIGB, thereby measuring the number of CCCLK clocks between TRIGA and TRIGB.
A 1 ps time measurement resolution between TRIGA and TRIGB is achieved by measuring the time difference between edges of the selected inputs TRIGA and TRIGB and the divided clock CCCLK (fine differences T.sub.fa and T.sub.fb, respectively, in FIG. 2) using interpolators 102 and 104 that have a resolution of 1 ps.
To control the interpolators 102 and 104, an event error detector 100 receives signals TRIGA and TRIGB as well as divided clocks CCLK and DCLK, both running at about 62.5 MHz. The signals CCLK and DCLK from the programmable frequency divider 116 are divided down from a 312.5-MHz master clock PFDCK.
The event error detector 100 outputs signals INTERP.sub.-- A (in response to activation of TRIGA) and INTERP.sub.-- B (in response to activation of TRIGB), which are provided to the interpolators 102 and 104, respectively. As shown in FIG. 2, the signal INTERP.sub.-- A is asserted high on the rising edge of the signal TRIGA. The signal INTERP.sub.-- A is maintained high until the occurrence of the second rising edge of DCLK after the leading edge of INTERP.sub.-- A. The signal INTERP.sub.-- B is asserted high on the rising edge of TRIGB, and INTERP.sub.-- B falls low on the second rising edge of DCLK after the leading edge of INTERP.sub.-- B. This guarantees that the width of the signals INTERP.sub.-- A and INTERP.sub.-- B are between 16 nanoseconds (ns) and 32 ns.
In response to assertion of the signals INTERP.sub.-- A and INTERP.sub.-- B, the two interpolators 102 and 104 generate signals AEN and BEN, respectively, for enabling fine counters 114 and 112. Each of the fine counters 114 and 112 is clocked by ACLK, which runs at the system oscillator clock frequency of 312.5 MHz. The interpolators 102 and 104 effectively stretch the signals INTERP.sub.-- A and INTERP.sub.-- B by a factor of 3200 for output as fine counter enable signals AEN and BEN to achieve a fine resolution of 1 ps.
As shown in FIG. 4A, each interpolator includes a ramp circuit 120 and a comparator 122 for comparing the output of the ramp circuit 120 with a reference voltage. The comparator 122 outputs the enable signal AEN or BEN to the fine counter 114 or 112.
The ramp circuit 120 includes the circuitry shown in FIG. 4B, which includes a first current source 142 that outputs a tiny current (e.g., 10 .mu.A), and a second, larger current source 144 capable of producing a relatively large current (e.g., 32 mA). The large current source 144 is connected to a node of a capacitor 140 by a switch 146, which is activated to ramp up the ramp circuit 120 in response to assertion of INTERP.sub.-- A or INTERP.sub.-- B. On assertion of INTERP.sub.-- A(B), the large current source 144 quickly charges the capacitor 140. When INTERPA(B) reaches a predetermined voltage, A(B)EN is activated. The capacitor 140 continues to charge until the signal INTERP.sub.-- A(B) is negated, at which time the ramp circuit 120 ramps down. The charging period is shown as period T.sub.0 in FIG. 4A.
During ramp down, the capacitor 140 is discharged by the tiny current source 142 at a much slower rate. The comparator 122 continues to drive the signal A(B)EN high until the capacitor 140 has discharged to a predetermined voltage, at which time the comparator 122 drives its output signal A(B)EN low. The discharge period is shown as period T.sub.1 in FIG. 4A.
By using a large current source of 32 mA and a tiny current source of 10 .mu.A, the ramp circuit 120 in effect stretches the input signal INTERP.sub.-- A(B) by a factor of 3200. Since the fine counter 114 or 112 runs at 312.5 MHz, the resolution achieved is 1 ps (or 1/(312.5 MHz*3200)).
Upon completion of the measurement, the contents of the fine counters 112 and 114, clocked by ACLK, and the coarse counter 110, clocked by the divided signal CCCLK, are retrieved by a readback logic block 118. The time difference between events A and B, TIMEAtoB, is calculated according to Equation 1: EQU TIMEAtoB=(COUNTA*1 ps)-(COUNTB*1 ps)+(COUNTC*16 ns), Eq. (1)
where COUNTA is the value in the fine counter 114, COUNTB is the value in the fine counter 112, and COUNTC is the value in the coarse counter 110.
In effect, the interpolator 102 in combination with the fine counter 114 measures the time difference between the leading edge of INTERP.sub.-- A and the next leading edge of the divided clock CCCLK (on which the coarse counter 110 is activated) at 1 ps resolution. Similarly, the interpolator 104 in combination with the fine counter 112 measures the time difference between the leading edge of INTERP.sub.-- B and the next leading edge of CCCLK, on which the coarse counter 110 is stopped.